The present invention relates to an electrically programmable read-only memory.
An electrically programmable read-only memory is commonly referred to as an EPROM or PROM, the latter term being used below. PROMs are fabricated in large numbers on semiconductor wafers, and are widely used in electronic computing devices for the storage of fixed data and programs.
There is no single standard power-supply voltage for electronic computing devices. Many operate on a five-volt (5-V) supply, but others operate on a lower-voltage supply such as a three-volt (3-V) supply. A PROM manufacturer normally provides different PROM versions specified for operation at different power-supply voltages. The different versions conventionally have the same circuit design, but differ in their wafer process parameters and programming parameters. For example, to ensure reliable operation, the thicknesses of oxide films deposited during the wafer process must be adjusted according to the power-supply voltage, and the programming voltage and the internal cell voltage used during programming must be optimized for each power-supply voltage. Optimization of these programming parameters is particularly difficult, requiring much time and labor in the design and development stage.
An object of the present invention is to provide a PROM having two different versions, specified for operation at two different power-supply voltages, both versions being manufactured with the same wafer process parameters and programmed with the same programming parameters.
An attendant object of the invention is to reduce PROM design and development costs.
Another object is to shorten PROM design and development time.
The invented PROM operates in a program mode and a read mode on a power supply. Either a first power-supply voltage or a second power-supply voltage is specified when the PROM is manufactured. The PROM has word lines, bit lines, memory cells, an address decoder, and word-line drivers. When selected by the address decoder, a word-line driver drives a word line to a potential that selects the memory cells disposed on the word line. The selected memory cells are programmed with data from the bit lines in the program mode, and supply the programmed data to the bit lines in the read mode.
The invention employs a method of driving the word lines in which a field-effect transistor of one type is used if the first power-supply voltage is specified, and a field-effect transistor of another type is used if the second power-supply voltage is specified. Both methods drive the word lines to the first power-supply voltage. The two transistors are, for example, a p-channel transistor and an n-channel transistor, or a depletion-mode transistor and an enhancement-mode transistor.
In a first aspect of the invention, each word-line driver includes a first node, a second node, four transistors, and a wiring pattern that can be configured in different ways by a fabrication mask option. The first node is coupled through the first transistor to the power supply, through the second transistor to ground, and by the wiring pattern to the second node if the first power-supply voltage is specified. The first and second nodes are mutually disconnected if the second power-supply voltage is specified. The second node is coupled through the third transistor to the power supply. The first node is coupled through the fourth transistor to a word line. The substrate of the first transistor is grounded.
In the read mode, a word line is driven through the second and fourth transistors or the first and fourth transistors, depending on the power-supply voltage specification. The grounded substrate of the first transistor provides a body effect that results in the word line being driven to the same potential in both cases.
In a second aspect of the invention, each word-line driver includes a transistor that supplies a decoded address signal to a word line, and a logic circuit that turns the transistor on and off according to the decoded address signal and the operating mode. The transistor is a depletion-mode transistor if the first power-supply voltage is specified, and an enhancement-mode transistor if the second power-supply voltage is specified.
In a third aspect of the invention, each word-line driver includes a transistor that supplies a decoded address signal to a word line, and a wiring circuit that supplies either a control signal or a predetermined potential to the gate electrode of the transistor, depending on the power-supply specification. The transistor is a depletion-mode transistor if the first power-supply voltage is specified, and an enhancement-mode transistor if the second power-supply voltage is specified.
In the second and third aspects of the invention, in the read mode, the enhancement-mode transistor used with the second power-supply voltage turns off when the word line reaches substantially the first power-supply voltage, so the selected word line is driven to substantially the first power-supply voltage regardless of which power-supply voltage is used.
In all aspects of the invention, since the word lines are driven to substantially the same potential regardless of which power-supply voltage is used, the PROM can be programmed with the same programming voltage for both power-supply voltages, and the same wafer process can be used for both power-supply voltages.